The discovery of the giant magnetoresistive (GMR) effect has led to the development of a number of spin-based electronic devices. The GMR effect is observed in certain thin-film devices that are made up of alternating ferromagnetic and nonmagnetic layers. In a typical device, the relative orientations of magnetic directions of the ferromagnetic layers define a binary state of the device. The resistance across a device is generally lowest when the magnetic directions of the ferromagnetic layers are in a parallel orientation and highest when the magnetic directions are in an antiparallel orientation. In a related device, the magnetic tunnel junction (MTJ), the nonmagnetic metal layer is replaced by a thin insulating layer. The tunneling current through this insulating layer can also be measured as a resistance that changes depending on the relative magnetization state of the two layers. The MTJ device generally produces a much larger resistance change than the GMR device.
One type of magnetoresistive device is commonly referred to as a “spin valve.” Such devices can be used as data storage elements in magnetic random access memory (MRAM) devices. In this regard, exemplary MRAM applications of magnetoresistive devices are described in U.S. Pat. Nos. 6,147,922; 6,175,525; 6,178,111; 6,493,258, and U.S. Pat. App. Pub. No. 2005/0226064, all of which are incorporated herein by reference.
A spin valve or an MTJ device typically includes two or more ferromagnetic layers that are separated by a thin layer of a non-magnetic material (either a metal or insulator) and also includes an antiferromagnetic layer that “pins” the magnetization direction of one of the ferromagnetic layers. FIG. 1A illustrates (in a simplified form) the layers in a typical spin valve 10 as seen from a side view. As shown in FIG. 1A, the spin valve 10 includes ferromagnetic layers 12 and 14 separated by a nonmagnetic layer 16. In a typical arrangement, one of the magnetic layers is configured to be a fixed layer 14. The fixed layer 14 is adjacent to an anti-ferromagnetic layer 18, such that the magnetization direction of the fixed layer 14 is “pinned” in a particular orientation. The arrow in the fixed layer 14 indicates an exemplary pinned orientation, though, in general, the orientation could be pinned in either direction. Thus, the magnetization direction of the fixed layer 14 remains relatively fixed when operational magnetic fields are applied to spin valve 10. A second magnetic layer 12 is termed a free layer 12. In contrast with the fixed layer 14, the magnetization direction of the free layer 12 is free to switch between parallel and antiparallel orientations, as indicated by the double-arrow symbol in the free layer 12. By applying an appropriate magnetic field to the spin valve 10, the magnetization direction of the free layer 12 can be inverted while the magnetization direction of the fixed layer 14 remains the same.
FIG. 1B shows a three-dimensional view of the spin valve 10 of FIG. 1A. As shown, the spin valve 10 has a hard-axis (short-axis) and an easy-axis (long-axis). In the absence of an applied magnetic field, the magnetization directions of both the free layer 12 and the fixed layer 14 run substantially parallel to the easy-axis.
Typically, a magnetic memory, such as a magnetic random access memory (MRAM) or a magnetic read only memory (MROM), comprises memory cells that include a GMR or MTJ based memory bit. In general, the resistive state of a bit will be associated with one of two logical states: a binary value of “0” or a binary value of “1.”
Unfortunately, as a memory is operated over time, the resistive states of a memory bit may degrade, causing a degree of uncertainty within a memory bit. For example, temperature variations may cause the resistance of a memory bit to shift. In addition, if the memory is exposed to an extreme environment, such as a radiation environment, the resistance of the memory bit may increase over time. If the resistance of a particular memory bit degrades too much, the memory bit may be indicative of an incorrect logical state. Consequently, if this fault is not corrected, the memory may produce a deleterious influence on downstream circuitry and applications that use the memory. Therefore, it is desirable to produce a memory that supports reliable data clearing and sanitization.